1. Field of the Invention
The present invention relates to a method for fabricating a thin film transistor (TFT) for a TFT liquid crystal display (hereinafter, referred to as a TFT-LCD) device and in particular, to a method for fabricating a TFT, which allows the amount of charge current supplied to the pixels to be increased. This is achieved by fabricating a channel of a TFT formed at an amorphous silicon active region so that its length is not greater than 4 μm. The channel according to the present invention is formed by using a mask having slits or other slit-type openings.
2. Description of the Background Art
In high resolution TFT-LCD devices, due to the TFT structure having gate electrodes with narrow widths, the amount of charge current supplied to the pixels via the TFT is relatively small and a relatively longer charging time is required compared to low resolution TFT-LCD devices. In a typical TFT, where an amorphous silicon is used for an active region, there are limits to improving the mobility of the electric charges because the mobility does not generally exceed 0.6 cm/Vs for amorphous silicon. Thus, to improve the mobility of electric charges, the length of the channel (formed between the source and drain regions, and above the gate electrode) has to be shortened. However, because the fabrication process of a TFT-LCD is performed on a substrate having a large surface area, it is not easy to apply conventional semiconductor fabrication techniques for TFT-LCD fabrication requiring a short length channel. For example, it is difficult to form a uniform photoresist and to properly perform photolithography on a large substrate area to obtain a short length channel.
For defining a channel region according to the conventional art, a conventional light transmittance mask (i.e., exposure mask) is used by relying upon the resolution of an exposure device. The method for fabricating a TFT according to the conventional art will be described in detail with reference to accompanying drawings.
FIGS. 1A–1D are sectional views sequentially illustrating the method for fabricating a TFT according to the conventional art.
As a first step (FIG. 1A), a gate electrode 2 is formed on a glass substrate 1, and a gate insulating layer 3, an amorphous silicon 4, and an n+ amorphous silicon 5 having a high density n-type ions injected therein are sequentially formed thereon. Then, patterning of the n+ amorphous silicon 5 and the amorphous silicon 4 is achieved by a photolithography process to form an active region above the gate insulting layer 3 corresponding to the upper portion of the gate electrode 2.
As a second step (FIG. 1B), a source 6A and a drain 6B are formed by depositing a metal on the upper surface of the above structure in FIG. 1A and then patterned to form respective portions separated by a certain distance from the center portion of the n+ amorphous silicon 5. The source and drain 6A, 6B extend over the end portions of the amorphous silicon 4 and the n+ amorphous silicon 5, and onto a portion of the gate insulating layer 3. Here, portions of the n+ amorphous silicon 5 exposed between the source and drain portion 6A, 6B, and an upper portion of the amorphous silicon 4 are etched to define a channel region.
As a third step (FIG. 1C), a passivation layer 7 is deposited onto the structure of FIG. 1B and a contact hole is formed through a portion of the passivation layer 7 using a photolithography process to expose an upper portion of the drain 6B.
As a fourth step (FIG. 1D), an ITO (Indium Tin Oxide) thin film 8 is deposited onto the structure of FIG. 1C and then patterned to form a pixel being connected with the exposed drain 6B.
Hereinafter, the method for fabricating a TFT in accordance with the conventional art will be described in more detail.
First, as depicted in FIG. 1A, a metal is deposited onto the upper portion of the glass substrate 1, a photoresist is coated on the upper portion of the metal, the photoresist coated on the upper portion of the metal is exposed and developed to form a photoresist pattern. The gate electrode 2 is formed by etching the metal by an etching process using the photoresist pattern as an etching mask, and the photoresist pattern is removed. Then, the insulating layer 3, the amorphous silicon 4 and the n+ amorphous silicon 5 are sequentially deposited on the above structure. A photoresist is coated onto the upper surface of the n+ amorphous silicon 5, then exposed and developed (using an exposure mask) to form a photoresist pattern at portions opposing the upper and surrounding areas of the gate electrode 2. Next, an active region is formed at the upper and surrounding areas of the gate electrode 2 by patterning the n+ amorphous silicon 5 and the amorphous silicon 4 using an etching process employing the photoresist pattern as an etching mask, and the photoresist pattern is then removed using a wet etchant, etchant gas or the like.
As depicted in FIG. 1B, a metal is deposited onto the structure of FIG. 1A, and then a photoresist is coated thereon. After forming a photoresist pattern upon exposure and development, the metal is etched using an etching process employing the photoresist pattern as an etching mask to form a source 6A and a drain 6B which are respectively separated by a certain distance above the center portion of the n+ amorphous silicon 5 and formed onto a portion of the gate insulating layer 3 at the sides of the active region.
Then the above etching process is continued so that portions of the n+ amorphous silicon 5 exposed between the source and drain 6A, 6B, and an upper portion of the amorphous silicon 4 under the n+ amorphous silicon 5 are etched to define a channel region.
Here, the etching mask that is used allows light to pass through to the channel region and to the regions adjacent to the source and drain 6A, 6B. For example, the mask can have light blocking portions 10 and light transmitting portions 20 as shown in FIG. 2, wherein the light blocking portions 10 block light from reaching the source and drain 6A, 6B. It can be understood that the light intensity and diffraction amount for the light passing through each of the light transmitting portions 20 formed in the mask is relatively equivalent, as shown in the graph of FIG. 2.
The minimum line length of the channel region that can be formed by the conventional etching mask depends on the resolution of the exposure device. However, using conventional techniques, it is currently impossible or at least very difficult to properly form photoresist patterns having a line length of less than 4 μm, and thus the channel to be formed under the photoresist pattern cannot have a length of less than 4 μm. The reason for this is because when the light transmittance region of the etching mask is less than 4 μm in size, the distribution for the amount of exposed light passing through the conventional etching mask is undesirably spread out and the etched portions are thus not sharply defined. As a result, portions of undesired photoresist may remain (i.e., the photoresist is not properly etched) due to overlapping of adjacent photoresist pattern portions, and thus the desired overall photoresist pattern may not be properly formed using conventional art techniques.
Next, as depicted in FIG. 1C, the passivation layer 7 is deposited onto the upper surface of the structure of FIG. 1B, and an upper portion of the drain 6B is exposed by forming a contact hole through the passivation layer 7 using a photolithography process.
Finally, as depicted in FIG. 1D, a pixel contacting the exposed drain 6B is formed by depositing an ITO thin film 8 at the upper surface of the structure of FIG. 1C and the patterning thereof is performed by a photolithography process.